You'll find stuff all about me here! Hope you enjoy.
My current research involves designing a robust instruction set with minimal hardware demand. PRECISE (Process Register Extensions for Collapsed Instruction Set Encoding) attempts to reduce instruction pressure in a system by reducing the binary demand of the instruction set. I work under the guidance of its contriver Thomas Sterling and Maciej Brodowicz. In Spring 2008 we published Improving Code Compression using Clustered Modalities in the proceedings of the 46th ACM Southeast Conference. The official citation has can be found here. You may find the slides of the presentation here.
I am also researching enabling architecture with the Xilinx ML506 evaluation platform. I have so far enabled the sending and receiving of an Ethernet packet to and from the copper+RJ45 using an example design from the Tri-mode Ethernet MAC IP. Though getting the design to work requires only several changes, they are not necessarily intuitive due to lack of documentation. If you have access to the PX SVN, you can see the MII implemented design here.
Under the guidance of my major professor David M. Koppelman, my doctoral research is in conventional CPU core architecture. It addresses an inherent overhead of control independence exploitation called branch weakening. I have recently passed my doctoral general exam by proposing research in this topic. You can find the proposal manuscript here as well as the slides I used for presentation here.
I gave my first lecture in Fall 2008 on the C programming language. You can find slides and the supplementary code here.